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數(shù)字邏輯是計算機(jī)專業(yè)的必修課程，本教材采用英文編寫，以邏輯代數(shù)的函數(shù)方法為基礎(chǔ)，通過大量實踐案例和集成電路芯片的應(yīng)用，系統(tǒng)介紹了數(shù)字邏輯的基本理論、數(shù)字電路的分析和設(shè)計方法。本教材共八章，內(nèi)容包含Number Systems and Codes、Logical Algebra、Digital Circuit、Combinational Logic Circuit、Flip-flop、Synchronous Sequential Logic Circuit、Verilog Implementation of Logic Circuit以及Memory and Programmable Logic Device。其中，Verilog Implementation of Logic Circuit與計算機(jī)學(xué)科后續(xù)課程（如計算機(jī)組成原理、計算機(jī)體系結(jié)構(gòu)、微機(jī)接口技術(shù)等）銜接緊密，能幫助學(xué)生準(zhǔn)備先導(dǎo)知識。本教材配套資源成熟，配有慕課視頻、PPT和授課大綱等數(shù)字化資源。本教材可作為高等學(xué)校計算機(jī)專業(yè)大類的本科生、留學(xué)本科生的數(shù)字邏輯課程教材，也可供從事數(shù)字電路研究與應(yīng)用的科技工作者學(xué)習(xí)參考。

Chapter One Number Systems and Codes 1.1 Number Systems 1.2 Number Conversion 1.3 Signed Binary Numbers 1.4 Addition and Subtraction of Signed Binary Numbers 1.5 Numerical Codes Exercise Chapter Two Logical Algebra 2.1 Three Basic Functions of Logical Algebra 2.2 Laws and Rules of Logical Algebra 2.3 Compound Functions of Logical Algebra 2.4 Positive Logic and Negative Logic 2.5 Forms and Transformation of Logic Function 2.6 Simplification of Logic Function by Formula 2.7 Simplification of Logic Function by Kmap Exercise Chapter Three Digital Circuit 3.1 CMOS Transistor 3.2 Basic Logic Gates Implemented by CMOS Transistor 3.3 Other Types of Logic Gates in Digital Circuit 3.4 Unused Input of CMOS Circuit 3.5 Electrical Characteristics 3.6 TTL Transistor 3.7 Interface Compatibility of CMOS and TTL Transistors Exercise Chapter Four Combinational Logic Circuit 4.1 Analysis of Combinational Logic Circuit 4.2 Design of Combinational Logic Circuit 4.3 Universal Logic Gates 4.4 Arithmetic Circuits 4.5 Code Converter 4.6 Numerical Comparator 4.7 Encoder 4.8 Decoder 4.9 4 to 1 Line Data Selector (Multiplexer) 4.10 Hazard of Combinational Logic Circuit Exercise Chapter Five Flip flop 5.1 Definition of Flip flop 5.2 RS Flip flop 5.3 D Flip flop 5.4 JK Flip flop 5.5 Integrated Flip flop 5.6 The Other Types of Flip flop 5.7 Conversion Between Different Types of Flip flops Exercise Chapter Six Synchronous Sequential Logic Circuit 6.1 Definition of Synchronous Sequential Logic Circuit 6.2 Analysis of Synchronous Sequential Logic Circuit 6.3 State Simplification 6.4 Counter 6.5 Register 6.6 ShiftRegister Counter 6.7 Sequence Generator 6.8 Sequence Detector 6.9 Code Detector Exercise Chapter Seven Verilog Implementation of Logic Circuit 7.1 Basic Programming Grammar of Verilog 7.2 Verilog Implementation of the Logic Gates 7.3 Verilog Implementation of the Combinational Logic Circuit 7.4 Verilog Implementation of the Flip flop 7.5 Verilog Implementation of the Synchronous Sequential Logic Circuit Exercise Chapter Eight Memory and Programmable Logic Device 8.1 PLD 8.2 ROM 8.3 RAM Exercise Bibliography

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